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p1/13 version 0.6 preliminary, sept 2011 ml2002 preliminary ml2002 series static/half duty lcd cog driver application general purpose clock high quality instrument telephone, mobile phone automotive handheld device like pda, mp3, or pmp features a gold bump chip which can reduce pin count and are a. simplest design with no charge pump to supply high voltage to lcd only 5 pin is needed which can reduce space. low operating current can disable internal clock to reduce current. wide logic & lcd power supply: 2.5v to 6.0v no need to add external voltage regulator static or 1/2 duty driving with 1/2 bias number of segments: (static) 48, (1/2 duty) 96 cascading structure to increase the number of driving segments, it?s more flexible for different application. build-in lcd voltage driver, crystal oscillator, internal rc oscillator and display control circuit. offer best contrast and widest viewing angle of tn lcd technology especially in static mode. no temperature compensation is needed for topr = -4 0 o c to 80 o c. ml2002 (cog) lcd driver can be cascaded to increase the numb er of segments drive, with static driving it can form a single piece of 48 (1 ics) or 96 (2 ic s cascaded) segments driver. with 1/2 duty, the number of segment drive would be doubled. it targets at custom tn lcd cog module product which requires the best quality of tn lcd technology and small to med ium number of segment display. ml2002 series driver offers the best contrast, the widest vie wing angle, the widest range of operating voltage and temperature when compared to the high duty cycle dr iver. emi and noise protection circuit has been added which tailor made for cog application. general description ordering information part number description package form ml2002-1u one ml2002 lcd driver gold bump die ml2002-2u two ml2002 lcd driver gold bump die
p2/13 version 0.6 preliminary, sept 2011 ml2002 preliminary absolute maximum ratings block diagram parameter symbol condition min max unit supply voltage v dd -0.5 +6.0 v supply current i dd v dd = 3v, no load -50 +50 ma input voltage v in gnd-0.3 v dd +0.3 v output voltage v out gnd-0.3 v dd +0.3 v dc input current i in -10 +10 ma dc output current i out -10 +10 ma storage temperature t stg -65 +150 o c total power dissipation p tot - 400 mw
p3/13 version 0.6 preliminary, sept 2011 ml2002 preliminary dc characteristic ac characteristic v dd = 3.0v; t amb = 25 o c ; unless otherwise specified parameter symbol condition min typ max unit supplies supply voltage v dd 2.5 - 6.0 v supply current i dd disable oscillator and 1/2 pvdd opamp - 0.1 0.5 ua supply current i dd enable oscillator - 25 60 ua supply current i dd enable oscillator and internal 1/2 pvdd opamp - 80 100 ua logic low-level input voltage v il gnd - 0.3*v dd v high-level input voltage v ih 0.7*v dd - v dd v low-level output current i ol v ol = 1.0v 1 - - ma high-level output current i oh v oh = 2.0v -1 - - ma lcd outputs output resistance at pads s1 to s40 r seg - 85 150 ohm output resistance at pads com1a and com1b r com - 45 100 ohm v dd =3.0v; t amb = 25 o c; unless otherwise specified parameter symbol conditions min typ max unit oscillator frequency at pad oout f oout 21 32 48 khz fin, load, din, dclk high time t h 0.4 - - us fin, load, din, dclk low time t l 0.4 - - us fin, load, din, dclk rise time t r - - 10 us fin, load, din, dclk fall time t f - - 10 us dclk frequency f dclk 1 - 250 khz
p4/13 version 0.6 preliminary, sept 2011 ml2002 preliminary with ms connected to gnd, it represents it is in slave mode, it will treat all the din data as display data and will be sent to ml2002?s display shift register directly through din and dclk. to load display data onto the screen, lai need to be high, the n a rising edge of dclk would load the display, the lai need to keep low again. there are 48 segments in static mode, and 96 segments in 1 /2 duty mode with 1/2 bias. the display data should be input in reverse order, for static it?s starting from seg48, seg47? seg2 to seg1, for 1/2 duty it?s starting from seg48-comb, seg48-coma ? seg1-comb to seg1-coma for proper display of data. when updating the display, it will require input ting 48 segments in static mode and 96 segments in 1/2 duty mode. i) internal power on reset at power on the ml2002 will reset the internal display data ram as cleared. timing diagram for slave mode display functional description
p5/13 version 0.6 preliminary, sept 2011 ml2002 preliminary ii) oscillator the lcd driving signal of ml2002 is clocked either by the built-in oscillator, crystal oscillator or from an external clock. a) internal clock when the internal oscillator is used, bioen should be connecte d to gnd and the oout should be connected to fin. the internal oscillator will oscillate at 32 khz and the frequency is independent in the range of 2.5v < v dd < 6.0v . then connect oout to fin. b) crystal clock when using the crystal oscillator, bcoen is connected to g nd, then connect the crystal to osc+, and osc-. then connect osc- to fin. the osc+ and osc- should connect as: c) external clock when using an external clock, bcoen & bioen is connected to vdd then connects the external clock to fin (32 khz) or lclk (125hz) iii) timing ml2002 have several frequencies of clock signal for the users t o choose for the lcd display clock (ie. lclk) and the blink clock (ie.bclk). they include the following clock signals: frequency of clock signal at fin = 32 khz actual divider of fin target input pin 256/128 hz 1/256(1/2 duty) or 1/128(static) lclk 128/64 hz 1/128(1/2 duty) or 1/64(static) 4 hz 1/8192 bclk 2 hz 1/16384 1 hz 1/32768 iv) segment outputs ml2002 has 48 segment outputs which should be connected directly to th e lcd. if less than 48 segments, the unused segments should be left open circuit. v) common outputs ml2002 consists of 2 common signals (ie. com1a & com1b). the common outputs should be left open-circuit if the outputs are unused. users can disable the com1a and com1b by connecting the a cen 1 and b cen 1 to vdd respectively. the common outputs will change to g nd after disabling it. vi) blink ml2002 has a blink function that users shall connect ben to gnd and input the blink clock (ie. bclk) either by connecting ml2002 output clock signal from frequ ency divider or an external clock signal. users shall disable blink function by connecting ben to vdd.
p6/13 version 0.6 preliminary, sept 2011 ml2002 preliminary chip size : part number description chip size ml2002-1u one ml2002 lcd driver 3660 x 660 ml2002-2u two ml2002 lcd driver 7320 x 660 chip thickness : 700 um + 25 um gold bump pad size : 32 um x 72 um gold bump height : 18 um + 2 um note : the die faces up in the diagram pad configuration
p7/13 version 0.6 preliminary, sept 2011 ml2002 preliminary pad orientation and alignment mark: note: pad 1, 49 and 50 are dum pads which must be open.
p8/13 version 0.6 preliminary, sept 2011 ml2002 preliminary ml2002 single chip connection 1. ml2002 1u static slave mode 2. ml2002 1u 1/2 duty slave mode application circuit
p9/13 version 0.6 preliminary, sept 2011 ml2002 preliminary ml2002 cascode structure connection 1. ml2002 2u 1/2duty-1/2duty slave-slave mode working glass size: length = 64.80 v.a width = 35.40 v.a (unit: mm)
p10/13 version 0.6 preliminary, sept 2011 ml2002 preliminary 2. ml2002 2u static slave-slave mode working glass size: length = 76.00 v.a width = 59.95 v.a (unit: mm)
p11/13 version 0.6 preliminary, sept 2011 ml2002 preliminary note : 1. in cascade format of ml2002(ie. ml2002-2u and ?3u), one pin is the input of current ml2002 and the other is for the connection with the corresp onding input pin of next ml2002. 2. condition : fin = 32 khz clock. pin description symbol pad description bres i e xternal reset input (active low) lgnd - logic ground int i alarm interrupt output lvdd - logic supply voltage ms i input ?0?, for slave mode din i data line input dclk i data clock input lai i/o it is an input pin which load the display o nto the lcd screen during rising edge. lao o send out load signal to the cascade slave ml2 002 for displaying data onto lcd screen. cei i enable chip for receive data/command in the din p in ceo o send out chip enable signal to the following cascad e slave ic dout o data output from the display data ram cnt i input clock, count number of rising edge cloc k q15 o output high on the 16 t h clock from cnt fin i 32768hz oscillator input 4,2,1hz o 4, 2, 1hz clock output 256/125 hz o 125hz clock output for static/ 250 clo ck output for 1/2 duty 125/62 hz o 62hz clock output for static/125 clock output for 1/2 duty lclk i lcd clock signal frequency seg1 .. seg48 o segment output com1a / b o common output pvdd - power vdd supply 1/2 pvdd i 1/2 pvdd lcd driving voltage 1/2 duty i ?1? ? halfduty, ?0? ? static a cen 1 , b cen 1 i common enable. ?0? ? enable, ?1? ? disable t0 i test mode. ? 0 ? ? normal mode, ? 1 ? ? testing mode oout o 32k internal clock output coen i crystal oscillator enable. ? 0 ? ? enable, ? 1 ? ? disable ioen i 32k internal clock enable. ? 0 ? ? enable, ? 1 ? ? disable hpvdden i 1/2 pvdd enable. ?0? ? enable, ?1? ? disable ben i blink control circuit enable ?0? ? enable, ?1? ? disable bclk i blink clock input osc+ / - i crystal oscillator input sync i/o to synchronize co mmon signal to the following cascade ic tfi i master mode 2/4 pin interface, ? 1 ? - 2pin , ? 0 ? - 4pin syen i sync enable. syen is ? 1 ? ? sync output, ? 0 ? ? sync will be high impredence. tout o when select 4pin interface, it would output timer d ata. dum1 ,2,3 - dummy pad, left it open only
p12/13 version 0.6 preliminary, sept 2011 ml2002 preliminary 1. to ensure the good flip-chip assembly quality, we suggest flip-chip bonding house add a ?check? pin for each cog module as shown on the section of ?appl ication example?. pin ?load? and pin ?check? shall be connected together if the flip-chip assembl y is in good condition. the measured resistance between pin ?load? and pin ?check? shall not m ore than 5 kohm. 2. the resistance of ito glass shall between 15 ohm/ to 25 ohm/ . 3. each common (ie. com1a and com1b) shall not cover more t han 2,000 mm 2 area. in case the viewing area of lcd has to be more than 2,000 mm 2 , ioen pin has to be connected to outside. at the time where data is transferring into the ic, internal oscill ator has to be disabled through ioen pin to prevent abnormal behavior. when data transfer finishes, inter nal oscillator has to be enabled again. suggested programming steps: 1 disable internal oscillator through ioen pin 2 delay (necessary for fast mcu) 3 transfer data through din, dclk, load 4 delay (necessary for fast mcu) 5 enable internal oscillator through ioen pin application note
p13/13 version 0.6 preliminary, sept 2011 ml2002 preliminary example : note : com1a and com1b shall cover half of the viewing area (ie. area = 1,300mm 2 ) each common shall not connect to each other. version 0.1 ? preliminary version 0.2 ? change alignment mark co-ordinate on page 7 add application note on page 12 modify application circuit on page 8 ? 10. updating feature list on page 1 updating functional description on page 4 version 0.3 ? change supply current condition with dis able oscillator and internal pvdd opamp remove real time clock in block diagram version 0.4 ? add application note when glass size area i s larger than 2000mm 2 for each com version 0.5 ? add timing diagram for using large lcd p anel version 0.6 ? add remark on page 8, for fin connect to gn d if oout don?t connect with fin. revision history

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